Using Dynamic-Length Vector Operations to Efficiently Emulate Fixed-Length Vector Operations

Abstract

Using vector registers can significantly enhance processor performance, especially in tasks that involve parallel data processing. To ensure code portability across different architectures, developers often use third-party libraries. These libraries abstract architecture-specific vector operations using high-level programming constructs. However, creating transparent wrappers over the base data types requires a deep understanding of both the library's features and the architectural differences between the vector extensions. This is especially important when porting to new platforms such as RISC-V, where the principles of working with vectors may differ significantly from other architectures.
This article reviews existing libraries for creating generalized vector algorithms and proposes solutions for adding support for the RISC-V vector extension to the EVE library, which is currently in active development. Although EVE supports scalable vectorization through SVE, integrating with RISC-V presents a number of additional challenges that need to be addressed. The main challenge is to efficiently utilize the unique features of RISC-V, such as the grouping of multiple vector registers. Additionally, we need to adapt existing libraries to work with the new hardware features. These features include limited vector operations that are not available at the architectural level.